Since the advent of multiple-layer metallization as an interconnect scheme for integrated circuits, there has been widespread technological focus and development efforts around deposition and characterization of reliable intermetal dielectric layers. As the dimensions of the interconnect architecture undergo progressive shrinkage, the use of organic polymer dielectrics to reduce capacitance, power consumption, and cross noise becomes all important. Functional and reliable integrated circuits require that throughout the fabrication sequence, hydrocarbon, ionic, and particulate contamination be held to a minimum. Current design schemes incorporate multi-layer circuit elements with densely packed, individual metal conductors encapsulated in dielectric materials. The metal conductors, or "lines", are often spaced less than 1Jm apart and are isolated by the dielectric, which is an effective insulator. During high temperature processing of a given layer, ionic contamination residing on the dielectric surface can diffuse into the bulk and destroy its integrity as an insulator. Sub-micron particles, if not removed, can create electrical shorts between adjacent metal lines and destroy the entire circuit. Also, contaminants adversely affect adhesion of further deposited films, mask semiconductor surfaces from reactive plasmas and chemistries necessary for further processing, and interfere with photolithography. Hence, precision cleaning methods are required throughout the IC fabrication sequence.
Organic polymers, specifically polyimides, have been used as integrated circuit intermetal dielectric materials (known as low .kappa. dielectric materials) since the early 1970s. Aromatic polyethers, such as poly(arylene ethers) are known to exhibit thermal stability comparable to polyimides but have ten to forty times lower moisture absorption, dielectric constants in the range of 2.35 to 2.80, and good retention of storage modulus above their glass transition temperature. These properties are relevant to enhanced circuit performance (higher speed, lower power consumption, and reduced signal to noise ratios), and processing cost (high throughput and simple methodologies). Given the current cost and complexity concerns regarding plasma chemical vapor deposition of dielectrics, the replacement of expensive plasma deposition equipment and complicated plasma processed, stacked dielectric sandwiches with a spin-on coating of low dielectric organic polymer dielectric films directly onto wafer substrates offers an attractive alternative. In particular, poly(arylene ether) polymers offer lower dielectric constants which render these compounds compatible with new sub micron geometries in semiconductor substrates.
In U.S. patent application Ser. No. 08/990,157 filed on Dec. 12, 1997 and owned by the instant assignee, there is disclosed a distinctive group of poly(arylene ethers), sold under the trademark FLARE.TM. which represents a new promising class of intermetal dielectrics for applications in submicron multilevel interconnects. Formulated with extremely low levels of metallic contamination in low toxicity organic solvents, FLARE solutions exhibit excellent shelf life and have very low moisture absorption. When spin coated onto metal or dielectric layers, such as titanium nitride or silicon dioxide, an extremely thin uniform film is adherently coated onto the metal or dielectric layer.
In the manufacture or integrated circuits, semiconductor wafer surface planarity is of extreme importance. To achieve the degree of planarity required to produce ultra high density integrated, chemical-mechanical polishing/planarization(CMP) is often employed. The terms "planarization" and "polishing" as used herein are interchangeable when referring to the technique of "CMP". In general, CMP involves holding a semiconductor against a moving polishing surface that is wetted with a chemically reactive slurry, containing abrasive materials such as silica or alumina. For example, a slurry tailored for silicon dioxide CMP is typically comprised of a colloidal suspension of silica particles in a KOH-based solution. The polishing surface is generally a planar pad made of relatively soft, porous material such as blown polyurethane and is usually mounted on a planar platen. One disadvantage of CMP is the high defect level observed on wafers after CMP processing. These defects on the semiconductor wafer typically correspond to submicron oxide (e.g. SiO.sub.2 or Al.sub.2 O.sub.3) particles from the polishing slurry that remains on the wafer surface after polishing. A primary concern with the use of CMP is the efficient and complete removal of the polishing slurry to prevent problems in subsequent processing steps.
After CMP, a water rinse and some form of mechanical agitation of the wafer surface is typically employed to remove slurry chemical and abrasive residue from the surface of the semiconductor wafer. Particle removal is greatly enhanced by the addition of mechanical shear forces and consequently mechanical brush scrubbing is now widely used as a means of post-CMP cleaning.
To aid particle removal in the post CMP mechanical process, process chemistry is typically employed in the form of highly basic (high pH) aqueous solutions introduced onto the mechanical brushes of the post-CMP clean. The solution reagents are typically water soluble amines or ammonia (NH.sub.4 OH). However such reagents have been found either ineffective or destructive when used to post-CMP clean organic dielectric films, particularly poly(arylene ether) dielectric films. These prior art amine or ammoniated reagents cause disruption of the organic coating adhesion and delamination of the dielectric organic polymer film layer from the underlying metal or dielectric substrate layer of the semiconductor wafer. Additionally, the low .kappa. organic polymeric dielectric layers have high surface tension properties such that the aqueous post-CMP clean solutions fail to wet (bead) the dielectric surface during mechanical brush cleaning thereby diminishing the effectiveness of the post-CMP clean.